1. Field of the Invention
The present invention relates to MOS transistors having a gate insulator comprising a dielectric of high permittivity and having a conductive gate comprising a titanium nitride layer (TiN). The present invention also relates to methods for depositing TiN layers.
2. Discussion of Prior Art
FIGS. 1A and 1B are a simplified cross-section view of a portion of a silicon wafer 1 on which a gate 2 of an N-channel MOS transistor and a gate 3 of a P-channel MOS transistor have been formed. Such gate structures are described in S. Baudot et al., “Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs”, Microelectronic Engineering, volume 88, pages 569-572, 2011 and in S. Baudot et al., “Understanding reversal effects of metallic aluminium introduced in HfSiON/TiN PMOSFETS”, Microelectronic Engineering, 2011.
In silicon wafer 1, a specific region, for example, an N-doped well 4, has been formed on the side of the P-channel MOS transistor.
The gate insulator of the N-channel and P-channel transistors comprises a dielectric layer 5, for example, nitrided silicon oxide, SiON, and a dielectric layer of high permittivity 6, for example, a layer of a hafnium-based material, for example HfSiON or HfO2.
Gate 2 of the N-channel transistor is formed of a very thin lanthanum layer 7, covered with a main TiN layer 8, itself coated with a polysilicon layer 9.
Gate 3 of the P-channel transistor further comprises, between layer 6 and layer 7, a first auxiliary TiN layer 10, an aluminum layer 11, and a second auxiliary TiN layer 12, to adjust the threshold voltage of the P-channel transistor with respect to that of the N-channel transistor.
As an example, for a transistor having a 28-nm gate length, the thickness of lanthanum layer 7 may be 0.4 nm, that of TiN layer 8 may be 6.5 nm, and that of polysilicon layer 9 may be 50 nm. The thickness of TiN layer 10 may be 1 nm, that of aluminum layer 11 may be 0.22 nm, and that of TiN layer 12 may be 2.5 nm.
It can be observed that transistors provided with a gate insulator and with a gate such as described hereabove have relatively high gate leakage currents. It can also be observed that the lifetime of such transistors is limited.
Thus, there is a need for transistors having a gate structure similar to that described in relation with FIGS. 1A and 1B but having a lower gate leakage current and a longer lifetime.